1. Field of the Invention
The present invention relates to peripheral device controllers used in computer systems, and more particularly to controllers having an onboard processor for local supervisory control and supervising a secondary bus.
2. Description of the Related Art
A common peripheral bus specification used for connecting disk drives, tape back-up units and other peripheral items to a computer system is the Small Computer System Interface or SCSI standard. The SCSI bus interface has been developing over a period of years and has entered a second generation referred to as SCSI-2. Up to seven different peripheral devices can be connected to a SCSI bus and be controlled through a single SCSI bus controller unit. In personal computers the SCSI bus controller is preferably in the form of a interchangeable circuit board or adapter which is installed in one of the slots in the personal computer. In this manner the microprocessor forming the basis of the personal computer system can interact with the SCSI bus controller and access the particular peripheral devices in a given installation.
One of the reasons for the growing interest in the SCSI bus is the relatively high data transfer rates which are available, particularly with the advent of higher performance peripheral devices. This interest is further enhanced by the development of intelligent bus mastering controller units which can be installed in the various newer computer buses, such as those according to the Extended Industry Standard Architecture (EISA) or the Micro Channel Architecture (MCA). The bus mastering chips allow very high data transfer rates between the memory in the personal computer and the local adaptor, and when combined with the high data rates possible in the SCSI bus, theoretically very high performance peripheral systems could be developed. However, one problem which develops relates to the transfer of data between the devices residing on the SCSI bus and the computer system bus. Because the two buses are operating asynchronously and at different data rates, it is required that some sort of buffering memory be utilized on the SCSI bus controller card. A further problem is that commands must also be transferred between the system and the SCSI bus and SCSI bus controller. If the main system processor is used to provide control of the various operations, then the performance of the bus controller is greatly diminished. If a local onboard processor is utilized, then performance can be improved, but the buffering problem still remains.
Conventionally, the local microprocessor is involved both in the transfer of the data from the SCSI bus and the transfer of data to the host bus, thus limiting data transfer operations to the effective speed of the local processor. Given the high data transfer rates possible on both the computer system bus and the SCSI bus, this inclusion of the local processor and its multiple operations generally results in reduction of the potential data rates. Therefore it is desirable that the local microprocessor be removed from the actual data transfer operations between the SCSI bus and the host computer bus, thus allowing higher data throughput.
One technique for resolving the problem has been the use of a caching controller, where large amounts of data are transferred into a cache memory on the controller and then transferred under control of the local microprocessor to the host system. The cache is sized so that a majority of the requests can be serviced from or by the cache, thus increasing computer system performance. But if a miss occurs, problems still exist. Additionally, large amounts of cache memory can be required, thus increasing expense.